The present invention relates to a block decoder of a flash memory device and, more particularly, to a block decoder of a flash memory device, which can increase the integration level of a flash memory device by reducing the number of control signals.
There has been an increasing demand for semiconductor memory devices which can be electrically programmed and erased and do not need a refresh function of rewriting data at specific intervals. In order to develop large-capacity memory devices capable of storing a large amount of data, research has been done on the high integration of memory devices, particularly flash memory.
Flash memory is generally categorized as NAND flash memory and NOR flash memory. NOR flash memory has a structure in which memory cells are independently connected to bit lines and word lines and therefore exhibits excellent random access time characteristics. NAND flash memory has a structure in which memory cells are connected in series, requiring only one contact per cell string, and therefore exhibits high integration characteristics. Accordingly, the NAND structure is generally used in high-integrated flash memory.
In general, a flash memory device requires a block decoder for selecting a memory cell array on a per block basis to perform program, read and erase operations of a memory cell.
FIG. 1 is a circuit diagram showing a block decoder of a conventional flash memory device.
Referring to FIG. 1, a NAND gate ND1 logically combines address signals XA, XB, XC and XD. A NAND gate ND2 logically combines an output signal of the NAND gate ND1 and a program precharge signal PGMPREb. When at least one of the address signals XA, XB, XC and XD is input at a low level, the NAND gate ND1 outputs a high-level signal. When at least one of the output signals of the NAND gate ND1 and the program precharge signal PGMPREb is input at a low level, the NAND gate ND2 outputs a high-level signal.
A NAND gate ND3 logically combines an output signal of the NAND gate ND2 and a block enable signal EN. When the block enable signal EN is applied at a low level, the NAND gate ND3 outputs a high-level signal to turn on a transistor N2. Thus, a node Q1 is reset.
A transistor N1 is turned in response to a precharge signal PRE such that the output signal of the NAND gate ND2 is applied to the node Q1. The potential of the node Q1 functions as a block select signal BLKWL. Transistors N3 and N4 are turned on in response to first and second control signals GA and GB at a pumping voltage (Vpp) level, respectively, such that the pumping voltage Vpp is applied to the node Q1. Thus, a block switch 20 operates in response to the potential of the node Qt, that is, the block select signal BLKWL. Accordingly, global word lines GWL<31;0> and word lines of a memory cell array 30 are connected.
FIG. 2 shows line arrangements of signals used in the block decoder circuit of FIG. 1.
Referring to FIG. 2, a plurality of metal lines for inputting signals to control a block decoder is arranged beside a plurality of memory blocks (for example, 2048 metal lines are provided). Of the plurality of metal lines, the metal lines for inputting address signals XA<7:0>, XB<7:0>, XC<7:0> and XD<3:0> include 28 lines for inputting coding signals to select a memory block. When the metal line has a line width of 0.5 μm and a distance between the lines is 0.5 μm, a total amount of space occupied by the metal lines is 28 μm.